Semiconductor devices, such as transistor structures, continue to be scaled to smaller dimensions as process lithography improves. However, different challenges have been encountered in the scaling of transistor structures much below 100 nm. Additionally, when transistor dimensions on the order of 100 nm and smaller are used, implants cannot be adequately controlled with conventional semiconductor fabrication equipment. Channel dopant fluctuations adversely affect device uniformity within circuits. To control a conventional bulk transistor's threshold voltage which is the voltage at which the transistor becomes conductive, dopants in the channel are used. However, channel doping is not an efficient method for ultra-thin devices due to the large amount of channel impurities that are required. Therefore, highly doped ultra-thin devices are even more susceptible to threshold voltage fluctuations. Additionally, high channel doping concentrations degrade both electron and hole mobility and promote source/gate and drain/gate junction leakage.
A technique to improve bulk transistor performance is to provide a bulk transistor having a strained channel. Such devices are structured to place a strain on the transistor's channel. An appropriately strained channel results in electron and hole mobility enhancement that increases the conduction current which provides a higher device drive performance.
One method to form a transistor having a strained channel is to recess silicon material in those areas where the source and drain are to be formed and re-grow a stressor material in the recessed areas. However, when thin-body devices are being implemented, the depth available for the stressor material is insufficient to adequately strain the channel. Another issue with this technique is that the silicon material is recessed with an etch process. Stopping the etch process at a desired depth is a challenge and subject to variation. Additionally, re-growth of the stressor material on the remaining ultra-thin silicon is problematic. Also, the ultra-thin silicon can agglomerate at temperatures required for growing the stressor material. Additionally, this method does not apply to the known FINFET structures or any thin-body transistor devices.
Another known method to induce stress into a channel is the use of a substrate as a stressor material. A shortcoming with this approach is that when the stressor material is SiGe, the SiGe causes degradation of the gate dielectric due to increased interface states when the Ge diffuses to the dielectric semiconductor interface. The material SiGe has a narrow bandgap. Therefore, another issue with this approach is that the presence of SiGe in the transistor's channel increases the transistor's off-state current leakage. Additionally, this method does not apply to the known FINFET structures or any vertical thin body double gate transistor.
Yet another known method of stressing a transistor channel is the use of overlying stress inducing layers over the active regions of the transistor. However, the stressor material is located far enough from the channel so that the influence of the stressor material on the channel is diminished.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.